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"From Fast to Faster: A Deep Dive into Memory System Speed Optimization"

Tuesday, 7 November 2023, 2pm ET

Memory interface speeds keep increasing to meet performance demand. For instance, DDR5 is 275% faster than DDR4, reaching 8800 MT/s or more. But higher speeds also complicate memory design and validation. To achieve the next memory standard, designers need a connected workflow that streamlines time-to-insight from concept to simulation and test.

In this webinar, you will learn from industry experts:

• Best practices pathfinding for complex modulation interfaces.
• Compensate for signal degradation with Decision Feedback Equalization.
• Optimize timing at higher frequencies by analyzing key sources of jitter.
• Improve analysis accuracy using probe models to account for equipment loading effects.

Speakers:

Hee-Soo Lee, SerDes/DDR Product Owner, EDA Software Group, Keysight Technologies

• Hee-Soo Lee is the SerDes/DDR product owner in the EDA Software group of Keysight Technologies DES division, located in Santa Rosa, California, USA. He has held several positions in Keysight Technologies, Agilent Technologies, and Hewlett-Packard, including consulting business manager, technical marketing lead, and field applications engineer since 1989. Before, he worked for Daeryung Ind. Inc. as an RF/MW circuit design engineer. He has over 30 years of design and simulation experience in RF, microwave, and high-speed digital designs. He graduated with a BSEE from Hankuk Aviation University, South Korea.

Randy White, Memory Solutions Program Manager, Keysight Technologies

• Randy White is the Memory Solutions Program Manager for Keysight Technologies. He is focused on test methodologies for emerging memory technologies in server, mobile, and embedded applications. Randy has spent the last 20 years investigating signal integrity measurement techniques, including de-embedding algorithms, measurement/model correlation, high-speed measurements for real-time & sampling oscilloscopes, and BERTs & AWGs. He has participated on many standards committees, including PCI-SIG, USB-IF, SATA-IO, and JEDEC, to help define new test methodologies. He is currently the chair of the JEDEC JC40.5 Logic Validation subcommittee. He graduated with a BSEE from Oregon State University.

Offered Free by: Keysight
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