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Mixed-Signal Verification of Analog IP using SystemVerilog: An Object-Oriented Approach
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"Mixed-Signal Verification of Analog IP using SystemVerilog: An Object-Oriented Approach"

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Join this webinar on how to write an OOP-style SystemVerilog testbench for analog/mixed-signal circuits. The key testbench components such as the test sequence, driver, monitor, and scoreboard are presented in a step-by-step manner. Using a digitally-programmable analog filter as an example, this webinar discusses ways of reaching 100% functional coverage over the digital modes as well as analog inputs with random/directed tests and analog assertion checks.


Offered Free by: Scientific Analog, Inc.
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